Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. Ser. No. 11/193,788, filed onJul. 28, 2005, now pending, which claims priority from Korean PatentApplication No. 2004-59856, filed on Jul. 29, 2004, all of which arehereby incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method ofmanufacturing the semiconductor device. More particularly, the presentinvention relates to a semiconductor device that includes a storage nodecontact plug and a capacitor, and a method of manufacturing thesemiconductor device.

BACKGROUND OF THE INVENTION

Semiconductor manufacturing technologies continue to evolve to providememory devices having increasingly higher storage capacity, integrationdensity, and response speed. Dynamic random access memory (DRAM) devicesare most widely used as memory for electric and electronic apparatusesbecause such devices can have high storage capacity and integrationdensity. A DRAM device memory cell typically includes one accesstransistor and one storage capacitor.

As the integration density of a DRAM device memory cell increases, thememory cell generally occupies less area on a semiconductor substrate.With less area, capacitors in the memory cells generally need improvedcapacitance characteristics.

The capacitance of a capacitor is increased either by using a dielectriclayer of a dielectric material that has a higher dielectric constant, orthe surface area of the capacitor can be increased. Some high dielectricmaterials that have been considered for use include Al2O3, Ta2O5, orHfO2. However, forming a capacitor with a material of high dielectricconstant is complex because of process variations that occur duringmanufacturing.

To increase the surface area of a capacitor, stacked, trench, andcylindrical type capacitors have been substituted for planar typecapacitors.

In the DRAM device, the capacitors are electrically connected tosource/drain regions of a semiconductor substrate. Consequently, thelocations of the capacitors are limited by the locations of thesesource/drain regions. When the spacing between adjacent capacitorsbecomes narrow, an electrical short between capacitors may occur morefrequently.

To overcome the above-mentioned problems, a conventional method that iscapable of ensuring an overlap margin is used. In this conventionalmethod, storage node electrodes have an effective area regardless of thelocations of drains, and are sufficiently spaced apart from each otherby expanding an upper portion of a storage node contact plug.

FIGS. 1 and 2 are cross-sectional views illustrating a conventional DRAMdevice that includes a storage node contact plug having an expandedupper portion. FIG. 1 is a cross-sectional view taken along a linesubstantially parallel to a word line structure of the DRAM device andFIG. 2 is a cross-sectional view taken along a line substantiallyparallel to a bit line structure of the DRAM device.

Referring to FIGS. 1 and 2, isolation layers 12 for defining an activeregion 14 are formed in a semiconductor substrate 10. A word linestructure 16 is formed on the semiconductor substrate 10. The word linestructure 16 includes a gate insulation layer pattern, a gate electrodepattern and a hard mask pattern sequentially stacked.

Source/drain regions (not shown) are formed in the active region 14 atboth sides of the word line structure 16. Generally, the source regionis electrically connected to a bit line structure 30 and the drainregion is electrically connected to a storage node electrode 38.

A first insulating interlayer 18 covers the word line structure 16.First and second contact pads 20 a and 20 b electrically connected tothe source/drain regions, respectively, are formed at both sides of theword line structure 16.

A second insulating interlayer 22 is formed on the first insulatinginterlayer 18. A bit line contact (not shown) electrically connected tothe first contact pad 20 a is formed through the second insulatinginterlayer 22.

The bit line structure 30 is formed on the second insulating interlayer22. The bit line structure 30 includes a barrier metal layer pattern 24,a tungsten layer pattern 26 and a capping layer pattern 28, sequentiallystacked. A lower face of the barrier metal layer pattern 24 partiallymakes contact with the bit line contact. Thus, the barrier metal layerpattern 24 is electrically connected to the source region via the bitline contact.

An insulation layer structure 36 covers the bit line structure 30. Theinsulation layer structure 36 includes a third insulating interlayer 32and an etching stop layer 34. The storage node contact plug 38 iselectrically connected to the first contact pad 20 a through theinsulation layer structure 36 and the second insulating interlayer 22.The storage node contact plug 38 has a rounded upper portion, resultingin a rounded Y-shape upper portion. A storage node electrode 40 isformed on the storage node contact plug 38.

The storage node electrode 40 may have a sufficient overlap margin withrespect to the storage node contact plug 3 8. Also, shorts between thestorage node electrodes 40 may be decreased.

However, while forming the storage node contact plug 38, which fills astorage node contact hole, the storage node contact plug 38 isexcessively planarized due to its rounded upper side profile.

Also, the storage node contact plugs 38 generally have widths Adifferent from each other due to polished amounts of the planarizationprocess, again, because of the rounded upper side profile. Inparticular, when the storage node contact plug 38 has a narrow width A,the overlap margin between the storage node electrode 40 and the storagenode contact plug 38 is reduced.

Further, to form the rounded upper portion of the storage node contacthole, the insulation layer structure 36 and the second insulatinginterlayer 22 are anisotropically etched by a dry etching process andare then isotropically etched by a wet etching process. However, it isvery difficult to establish recipes of the wet etching process forpreventing adjacent storage contact holes from being in communicationwith each other and the bit line structure 30 from being exposed.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a semiconductor device thathas a sufficient overlap margin between a storage node contact plug anda storage node electrode.

Embodiments of the present invention also provide a method ofmanufacturing the above-mentioned semiconductor device.

A semiconductor device in accordance with one embodiment of the presentinvention includes a word line structure that extends in a firstdirection on an active region defined on a substrate. First and secondcontact pads are formed in the active region at both sides of the wordline structure. Bit line structures are electrically connected to thefirst contact pad and extend in a second direction substantiallyperpendicular to the first direction. An insulation layer structure isformed on the substrate having the bit line structures. A storage nodecontact plug is electrically connected to the second contact pad throughthe insulation layer structure. A storage node electrode is formed onthe storage node contact plug. The storage node contact plug is arrangedbetween the bit line structures. The storage node contact plug has alower portion and an upper portion having a width wider than that of thelower portion. The upper portion of the storage node contact plugextends in the second direction and has a vertical side facesubstantially perpendicular to the first direction.

According to some of the embodiments of the present invention, the upperportion of the storage node contact plug has a vertical side profile.Thus, the upper portion of the storage node contact plug has a uniformwidth regardless of a difference of polished amounts so that asufficient overlap margin between the storage node electrode and thestorage node contact plug may be provided. Also, the storage nodecontact hole having the upper portion is formed using the etching stoplayer so that recipes of a wet etching process may be readilyestablished.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings wherein:

FIGS. 1 and 2 are cross-sectional views illustrating a conventional DRAMdevice having an expanded upper portion;

FIG. 3 is a perspective view illustrating a semiconductor device inaccordance with an embodiment of the present invention;

FIGS. 4 to 10 are plan views illustrating a method of manufacturing thesemiconductor device in FIG. 3;

FIGS. 11 to 30 are cross-sectional views illustrating a method ofmanufacturing the semiconductor device in FIG. 3;

FIG. 31 is a perspective view illustrating a contact plug in accordancewith another embodiment of the present invention;

FIGS. 32 to 49 are cross-sectional views illustrating a method ofmanufacturing the contact plug in FIG. 31;

FIG. 50 is a perspective view illustrating a DRAM device in accordancewith yet another embodiment of the present invention; and

FIGS. 51 to 70 are cross-sectional views illustrating a method ofmanufacturing the DRAM device in FIG. 50;

DESCRIPTION OF THE EMBODIMENTS

The present invention is described more fully hereinafter with referenceto the accompanying drawings, in which embodiments of the invention areshown. This invention may, however, be embodied in many different formsand should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of theinvention to those skilled in the art. In the drawings, the size andrelative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or a layer is referred to asbeing “on”, “connected to”, or “coupled to” another element or layer, itcan be directly on, connected, or coupled to the other element or layer,or intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”,or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer, or section discussed below could be termed a secondelement, component, region, layer, or section without departing from theteachings of the present invention.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “includes”and/or “including”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 3 is a perspective view illustrating a semiconductor device inaccordance with an embodiment of the present invention.

Referring to FIG. 3, a plurality of isolation layers 102 is formed in asemiconductor substrate 100 to define a plurality of active regions 104on the semiconductor substrate 100. A plurality of word line structures106 is formed on the semiconductor substrate 100. The word linestructures 106 extend in a first direction traversing the active regions104. The word line structures 106 include a gate insulating layerpattern, a gate electrode pattern and a hard mask pattern sequentiallystacked.

A plurality of source regions 107 a and a plurality of drain regions 107b are formed in the active regions 104 at both sides of the word linestructures 106. The source regions 107 a positioned in a central portionof the active regions 104 correspond to regions to which bit linestructures are electrically connected. The drain regions 107 bpositioned at both sides of the active regions 104 correspond to regionsto which a storage node electrode is electrically connected.

A first insulating interlayer 108 at least partially covers the wordline structures 106. First and second contact pads 110 a and 110 b areelectrically connected to the source region 107 a and the drain region107 b,respectively.

A second insulating interlayer pattern 112 a is formed on the first andsecond contact pads 110 a and 110 b and the word line structures 106. Aplurality of bit line structures 122 a is formed on the secondinsulating interlayer 112 a and is electrically connected to the firstcontact pad 110 a. The bit line structures 122 a extend in a seconddirection substantially perpendicular to the first direction, and areelectrically isolated from the word line structures 106.

The bit line structures 122 a include a barrier metal layer pattern 116,a metal layer pattern 118, and a capping layer pattern 120 a. A spacer126 a is formed on both sides of the barrier metal layer pattern 116,the metal layer pattern 118, and the capping layer pattern 120 a. Here,the capping layer pattern 120 a and the spacer 126 a may include siliconnitride.

An insulation layer structure 132 c is formed on the second insulatinginterlayer pattern 112 a having the bit line structures 122 a. Theinsulation layer pattern 132 c includes a third insulating interlayerpattern 126 a, an etching stop layer pattern 128 b and a fourthinsulating interlayer pattern 130 b.

The third insulating interlayer pattern 126 a is formed on the secondinsulating interlayer pattern 112 a to partially fill a lower spacebetween the bit line structures 122 a. Also, the third insulatinginterlayer pattern 126 a has an upper face that is positioned on a planesubstantially identical to or higher than that of an upper face of themetal layer pattern 118.

The third insulating interlayer pattern 126 a suppresses generation of aparasite capacitance caused by the metal layer pattern 118. Thus, thethird insulating interlayer pattern 126 a may include a material havinga low dielectric constant, for example, silicon oxide.

The etching stop layer pattern 128 b is formed on a sidewall of the bitline structures 122 a exposed through the third insulating interlayerpattern 126 a. The etching stop layer pattern 128 b has a lower facethat is positioned on a plane substantially identical to or higher thanthat of the upper face of the metal layer pattern 118.

The fourth insulating interlayer pattern 130 b is formed on the etchingstop layer pattern 128 b to partially fill an upper portion of the spacebetween the bit line structures 122 a.

A plurality of storage node contact plugs 142 is formed through theinsulation layer structure 132 c, the second insulating interlayerpattern 112 a and the bit line structures 122 a, and is electricallyconnected to the second contact pad 110 b. The storage node contactplugs 142 are positioned between the bit line structures 122 a. Thestorage node contact plugs 142 have a lower portion and an upper portionwider than the lower portion. Also, the upper portion of the storagenode contact plugs 142 extends in the second direction and has avertical side face substantially perpendicular to the first direction.

A plurality of storage node electrodes 144 is formed on the storage nodecontact plugs 142. The storage node electrodes 144 may have a concaveshape or a cylindrical shape. The storage node electrodes 144 correspondto the storage node contact plugs 142. Also, the storage node electrodes144 are arranged in a zigzag pattern on the respective storage nodecontact plugs 142. In particular, a straight line connected between theadjacent storage node electrodes 144 is diagonal to the first and seconddirections.

According to the semiconductor device of the present embodiment, theupper portion of the storage node contact plug 142 extends in the seconddirection and has a substantially vertical side face B so that the upperportion of the storage node contact plug 142 has a uniform width Cregardless of a difference of polished amounts, during a planarizationprocess. As a result, a sufficient overlap margin between the storagenode electrode 144 and the storage node contact plug 142 may be ensured.

FIGS. 4 to 10 are plan views and FIGS. 11 to 30 are cross-sectionalviews, together illustrating a method of manufacturing the semiconductordevice in FIG. 3. FIGS. 11, 13, 15, 17, 19, 21, 23, 25, 27 and 29 arecross-sectional views taken along line I-I′ in FIG. 3; and FIGS. 12, 14,16, 18, 20, 22, 24, 26, 28 and 30 are cross-sectional views taken alongline II-II′ in FIG. 3. Referring to FIG. 4, the isolation layers 102 areformed in the semiconductor substrate 100 by a shallow trench isolation(STI) process to define the active regions 104 having a T shape. Also,to position the active regions 104 in a restricted region, the activeregions 104 are arranged in a zigzag pattern.

Referring to FIG. 5, the word line structures 106 are formed on thesemiconductor substrate 100. The word line structures 106 extend in thefirst direction traversing the active regions 104. The word linestructures 106 include the gate insulating layer pattern, the gateelectrode pattern and the hard mask pattern sequentially stacked. Here,one active region 104 includes two word line structures 106 arranged inparallel to each other so that two unit cells are formed in one activeregion 104.

Impurities are implanted into the semiconductor substrate 100 using theword line structures 106 as an ion implantation mask to form the sourceregions 107 a and the drain regions 107 b in the active regions 104 atboth sides of the word line structures 106. The source regions 107 apositioned in a central portion of the active regions 104 correspond toregions to which bit line structures are electrically connected. Thedrain regions 107 b positioned at both sides of the active regions 104correspond to regions to which a storage node electrode is electricallyconnected.

Referring to FIG. 6, a first insulating interlayer (not shown) coversthe word line structures 106. The first insulating interlayer ispartially etched to form self-aligned contact holes exposing the sourceregion 107 a and the drain region 107 b. The contact holes are filledwith doped polysilicon to form the first contact pads 110 a and thesecond contact pads 110 b electrically connected to the source region107 a and the drain region 107 b, respectively.

Referring to FIG. 7, a second insulating interlayer (not shown) isformed on the first insulating interlayer including the first and secondcontact pads 110 a and 110 b. The second insulating interlayer ispartially etched to form bit line contact holes 114 exposing the firstcontact pads 110 a.

Referring to FIG. 8, the bit line structures 122 a are formed on thesecond insulating interlayer to fill the bit line contact holes 114. Thebit line structures 122 a are electrically connected to the firstcontact pad 110 a, and are electrically isolated from the word linestructures 106, and extend in the second direction. The bit linestructures 122 a include the barrier metal layer pattern, the tungstenlayer pattern, and the capping layer pattern sequentially stacked. Aspacer (not shown) is formed on sidewalls of the barrier metal layerpattern, the tungsten layer pattern, and the capping layer pattern.

Referring to FIG. 9, the insulation layer structure (not shown) isformed on the second insulating interlayer having the bit linestructures 122 a. The insulation layer structure includes the thirdinsulating interlayer pattern, the etching stop layer pattern, and thefourth insulating interlayer pattern. A mask pattern 150 includingpolysilicon is formed on the insulation layer structure. The maskpattern 150 covers the first contact pad 110 a, partially exposes thesecond contact pad 110 b, and extends in the first direction.

Referring to FIG. 10, the insulation layer structure is partially etchedusing the mask pattern as an etching mask to form the storage nodecontact holes (not shown) having the lower portion and the upper portionwider than the lower portion. The upper portion of the storage nodecontact holes extends in the second direction and has the vertical sideface substantially perpendicular to the first direction. The storagenode contact holes are filled with a conductive material to form thestorage contact plugs 142.

The storage node electrodes 144 having a cylindrical shape are formed onthe storage node contact plugs 142. The storage node electrodes 144 mayhave a concave shape or a cylindrical shape. The storage node electrodes144 correspond to the storage node contact plugs 142. Also, the storagenode electrodes 144 are arranged in a zigzag pattern on the respectivestorage node contact plugs 142. In particular, a straight line connectedbetween the adjacent storage node electrodes 144 is diagonal to thefirst and second directions.

A dielectric layer (not shown) and a plate electrode (not shown) aresequentially formed on the storage node electrode 144 to complete acapacitor (not shown).

Meanwhile, referring to FIGS. 11 and 12, a buffer oxide layer (notshown) is formed on the semiconductor substrate 100. The buffer oxidelayer functions to relieve stresses generated in forming a siliconnitride layer (not shown). The silicon nitride layer is formed on thebuffer oxide layer. The silicon nitride layer is dry etched to form asilicon nitride layer pattern (not shown). The buffer oxide layer is dryetched using the silicon nitride layer pattern as an etching mask toform a buffer oxide layer pattern (not shown). The semiconductorsubstrate 100 is etched using the silicon nitride layer pattern as anetching mask to form a trench (not shown) at a surface portion of thesemiconductor substrate 100. The trench is filled with a silicon oxidelayer (not shown). The silicon oxide layer is planarized to expose thesilicon nitride layer pattern. The silicon nitride layer pattern and thebuffer oxide layer pattern are removed by a wet etching process tocomplete the isolation layers 102 defining the active regions 104 of thesemiconductor substrate 100.

A surface of the active regions 104 is thermally oxidized to form a thingate insulation layer (not shown). A gate electrode layer (not shown)and a hard mask layer (not shown) are sequentially formed on the gateinsulation layer. The hard mask layer, the gate electrode layer and thegate insulation layer are patterned to form the word line structures106.

The impurities are implanted into the active regions 104 at both sidesof the word line structures 106 using the word line structures 106 as anion implantation mask to form the source regions 107 a and the drainregions 107 b.

The first insulating interlayer 108 covers the word line structures 106.The first insulating interlayer 108 is partially etched to form theself-aligned contact holes exposing the source region 107 a and thedrain region 107 b. The contact holes are filled with the dopedpolysilicon layer. The doped polysilicon layer is planarized until theword line structures 106 are exposed to form the first contact pads 110a and the second contact pads 110 b electrically connected to the sourceregion 107 a and the drain region 107 b, respectively.

The second insulating interlayer 112 is formed on the first insulatinginterlayer 108 including the first and second contact pads 110 a and 110b. The second insulating interlayer 112 is partially etched to form bitline contact holes (not shown) exposing the first contact pads 110 a.

A barrier metal layer (not shown) is formed in the bit line contactholes and on the second insulating interlayer 112. Examples of thebarrier metal layer are a titanium layer, a titanium nitride layer, atantalum layer, a tantalum nitride layer, a combination thereof, etc. Atungsten layer (not shown) is formed on the barrier metal layer. Acapping layer (not shown) including silicon nitride is formed on thetungsten layer.

Here, the capping layer functions as a hard mask in etching the tungstenlayer and a protection layer for protecting the tungsten layer informing a self-aligned contact. Thus, for a sufficient thickness of thecapping layer to remain after completing the process for etching thetungsten layer and the process for forming the self-aligned contact, thecapping layer is relatively thick. In the present embodiment, thecapping layer has a thickness of no less than two times that of thetungsten layer.

A first photoresist pattern (not shown) is formed on the capping layer.The capping layer is partially etched using the first photoresistpattern as an etching mask to form the capping layer pattern 120. Thefirst photoresist pattern is then removed. The tungsten layer and thebarrier metal layer are anisotropically etched using the capping layerpattern 120 as an etching mask to form the bit line structures 122including the barrier layer pattern 116, the tungsten layer pattern 118and the capping layer pattern 120.

The spacer 124 is formed on the sidewalls of the barrier layer pattern116, the tungsten layer pattern 118, and the capping layer pattern 120.

Referring to FIGS. 13 and 14, a third insulating interlayer (not shown)is formed on the second insulating interlayer 112 to fill a spacebetween the bit line structures 122. Here, the third insulatinginterlayer may include an insulation material having a dielectricconstant lower than that of silicon nitride, such as silicon oxide. Thethird insulating interlayer is planarized by a CMP process to expose thecapping layer pattern 120. Here, when the third insulating interlayer isplanarized by the CMP process, a height of the remaining thirdinsulating interlayer may be accurately measured.

The planarized third insulating interlayer is wet etched to form thethird insulating interlayer 126, partially filling a lower portion ofthe space between the bit line structures 122. Here, the thirdinsulating interlayer 126 has an upper face higher than that of thetungsten layer pattern 118.

Referring to FIGS. 15 and 16, the etching stop layer 128 is formed onthe third insulating interlayer 126 and the bit line structures 122. Theetching stop layer 128 may include a material having an etchingselectivity with respect to the third insulating interlayer 126, such assilicon nitride.

Referring to FIGS. 17 and 18, a fourth insulating interlayer (not shown)is formed on the etching stop layer 128 to fill the space between thebit line structures 122. The fourth insulating interlayer is planarizedby a CMP process until the etching stop layer 128 is exposed, to formthe fourth insulating interlayer 130, thereby completing the insulationlayer structure 132, including the third insulating interlayer 126, theetching stop layer 128 and the fourth insulating interlayer 130.

Referring to FIGS. 19 and 20, a mask layer (not shown) includingpolysilicon is formed on the fourth insulating interlayer 130 and theetching stop layer 128. A photoresist pattern (not shown) covering thefirst contact pad 110 a and exposing the second contact pad 110 b isformed on the mask layer. The mask layer is etched using the photoresistpattern as an etching mask to form the mask pattern 150. The photoresistpattern is then removed by a stripping process and/or an ashing process.

Referring to FIGS. 21 and 22, the fourth insulating interlayer 130 isanisotropically etched using the mask pattern 150 as an etching maskuntil the etching stop layer 128 is exposed to form the fourthinsulating interlayer pattern 130 a having a plurality of first openings134. Simultaneously, the etching stop layer 128 is anisotropicallyetched to form the preliminary etching stop layer pattern 128 a. Sincethe etching stop layer 128 functions to stop the anisotropic etchingprocess, the first openings 134 may have uniform depths.

Referring to FIGS. 23 and 24, the fourth insulating interlayer pattern130 a is isotropically etched to form a plurality of second openings 136having side faces B, and resulting in the formation of fourth insulatinginterlayer pattern 130 b. The side faces B of the second openings 136horizontally expand in opposite directions and have a vertical profile.The isotropic etching process may include a wet etching process. Sincethe third insulating interlayer 126 functions to stop the isotropicetching process, recipes of the wet etching process may be readilyselected.

Referring to FIGS. 25 and 26, the etching stop layer 128 exposed throughthe second openings 136, the third insulating interlayer 126 and thesecond insulating interlayer 112 are partially etched using the maskpattern as an etching mask to form a plurality of third openings 138.Here, the preliminary etching stop layer pattern 128 a, the spacer 124and the capping layer pattern 120 exposed through the mask pattern 150are anisotropically etched to self-align the third openings 138 by thepreliminary etching stop layer pattern 128 a, and to form the etchingstop layer pattern 128 b and the third insulating interlayer pattern 126a. The second and third openings 136 and 138 are referred to as thestorage node contact holes 140.

Referring to FIGS. 27 and 28, the storage node contact holes 140 arefilled with a conductive material including doped polysilicon. Theconductive material and the mask pattern 150 are planarized by a CMPprocess or an anisotropic etching process to form the storage nodecontact plugs 142. Here, since the side faces B of the storage nodecontact holes 140 have vertical profiles, the storage node contact plugs142 include upper faces having uniform widths C regardless of polishedamounts of the CMP process.

Referring to FIGS. 29 and 30, the storage node electrodes 144 are formedon the storage node contact plugs 142. The storage node electrodes 144correspond to the storage node contact plugs 142. Also, the storage nodeelectrodes 144 are arranged in a zigzag pattern on the storage nodecontact plugs 142. In particular, a straight line connected between theadjacent storage node electrodes 144 is diagonal to the first and seconddirections.

Since the upper faces of the storage node contact plugs 142 have uniformwidths C, the overlap margin between the storage node electrodes 144 andthe storage node contact plugs 142 may be sufficiently ensured. Also,since the etching stop layer 128 is formed on the bit line structures122 a covered by the mask pattern 150, the likelihood of a short betweenthe bit line structures 122 a and the storage node electrodes 144 may besuppressed.

The dielectric layer (not shown) and the plate electrode (not shown) aresequentially formed on the storage node electrode 144 to complete acapacitor (not shown).

FIG. 31 is a perspective view illustrating a contact plug in accordancewith another embodiment of the present invention;

Referring to FIG. 31, linear conductive structures 206 are formed on asemiconductor substrate 200. The conductive structures 206 include aconductive layer pattern 202 and a capping layer pattern 204. Theconductive layer pattern 202 includes a barrier metal layer pattern 202a and a metal layer pattern 202 b.

A nitride spacer 208 and a first insulating interlayer pattern 210 apartially cover the conductive structures 206. Particularly, the firstinsulating interlayer pattern 210 a encloses part of the conductivelayer pattern 202.

An etching stop layer pattern 212 b is formed on the first insulatinginterlayer pattern 210 a and encloses upper side faces of the conductivestructures 206. A second insulating interlayer pattern 214 b is formedon the etching stop layer pattern 212 b to separate the conductivestructures 206 from each other. Contact plugs 226 are formed through thefirst and second insulating interlayer patterns 210 a and 214 b betweenthe conductive structures 206. Here, the contact plugs 226 have a lowerportion and an upper portion wider than the lower portion. Also, thecontact plugs 226, having substantially vertical and planar side faces,have a width longer than its height.

FIGS. 32 to 49 are cross-sectional views illustrating a method ofmanufacturing the contact plug in FIG. 31. FIGS. 32, 34, 36, 38, 40, 42,44, 46 and 48 are cross-sectional views taken along line III-III′ inFIG. 31, and FIGS. 33, 35, 37, 39, 41, 43, 45, 47 and 49 arecross-sectional views taken along line IV-IV′ in FIG. 31.

Referring to FIGS. 32 and 33, a conductive layer (not shown) and acapping layer (not shown) are sequentially formed on the semiconductorsubstrate 200. The conductive layer and the capping layer are patternedto form the linear conductive structures 206, including the conductivelayer pattern 202 and the capping layer pattern 204. The conductivelayer pattern 202 includes a barrier metal layer pattern 202 a and ametal layer pattern 202 b. Examples of the barrier metal layer pattern202 a may include a titanium layer, a titanium nitride layer, acombination thereof, etc. An example of the metal layer pattern 202 b isa tungsten layer. An example of the capping layer pattern 204 is asilicon nitride layer.

Referring to FIGS. 34 and 35, a silicon nitride layer (not shown) isformed on the semiconductor substrate 200 along the conductivestructures 206. The silicon nitride layer is anisotropically etched toform the spacer 208. A first insulating interlayer (not shown) includingsilicon oxide covers the conductive structures 206 having the spacer208. The first insulating interlayer is planarized via a CMP processuntil the conductive structures 206 are exposed. The planarized firstinsulating interlayer is anisotropically etched to form the firstinsulating interlayer pattern 210 partially filling a lower spacebetween the conductive structures 206. Here, the first insulatinginterlayer pattern 210 has an upper face higher than that of the metallayer pattern 202 b.

Referring to FIGS. 36 and 37, the etching stop layer 212 includingsilicon nitride is formed on the conductive structures 206 and the firstinsulating interlayer pattern 210.

Referring to FIGS. 38 and 39, a second insulating interlayer 214 isformed on the etching stop layer 212 to fill the space between theconductive structures 206. The second insulating interlayer 214 and theetching stop layer 212 are planarized until the conductive structures206 are exposed to form the preliminary etching stop layer pattern 212a.

Referring to FIGS. 40 and 41, a mask layer (not shown) includingpolysilicon is formed on the planarized second insulating interlayer214. The mask layer is patterned to form a mask pattern 216 for definingcontact holes between the conductive structures 206.

Referring to FIGS. 42 and 43, the second insulating interlayer 214 isanisotropically etched using the mask pattern 216 as an etching mask toform a preliminary second insulating interlayer pattern 214 a havingfirst holes 218 that exposes the preliminary etching stop layer pattern212 a.

Referring to FIGS. 44 and 45, the preliminary second insulatinginterlayer pattern 214 a exposed through the first hole 218 is partiallyand isotropically etched by a wet etching process to form the secondinsulating interlayer pattern 214 b having second holes 220 that expandfrom the first holes 218 in a direction D, shown in FIG. 45. Here, thesecond insulating interlayer pattern 214 b partially remains between thesecond holes 220.

Referring to FIGS. 46 and 47, the preliminary etching stop layer pattern212 a and the first insulating interlayer pattern 210 exposed throughthe second holes 220 are anisotropically etched to form third holes 222having a volume smaller than that of the second holes 220, the firstinsulating interlayer pattern 210 a and the etching stop layer pattern212 b. Here, the third holes 222 have an opened upper end narrower thanthat of the second holes 220. The second and third holes 220 and 222 arereferred to as the contact hole 224.

Referring to FIGS. 48 and 49, the contact hole 224 is filled with aconductive material. The conductive material and the mask pattern 216are planarized to form the contact plugs 226.

FIG. 50 is a perspective view illustrating a DRAM device in accordancewith yet another embodiment of the present invention.

Referring to FIG. 50, an isolation layer 302 is formed in asemiconductor substrate 300 to define an active region 304 on thesemiconductor substrate 300. Word line structures 306 and contact pads308 are formed on the semiconductor substrate 300.

A first insulating interlayer pattern 310 a is formed on the contactpads 308 and the word line structures 306. Bit line structures 316 areformed on the first insulating interlayer 310 a. The bit line structures316 include a conductive layer pattern 312 and a capping layer pattern314. The conductive layer pattern 312 includes a barrier metal layerpattern 312 a and a metal layer pattern 312 b.

A spacer 318 and a second insulating interlayer pattern 320 a partiallycover the bit line structures 316. Particularly, the second insulatinginterlayer pattern 320 a encloses the conductive layer pattern 312.

An etching stop layer pattern 322 b is formed on the second insulatinginterlayer pattern 320 a and encloses upper side faces of the bit linestructures 316. A third insulating interlayer pattern 324 b is formed onthe etching stop layer pattern 322 b to separate the bit line structuresfrom each other. Contact plugs 336 are formed through the first, second,and third insulating interlayer patterns 310 a, 320 a and 324 b betweenthe bit line structures 316. Inclined storage node contact pads 338 areformed on the contact plugs 336.

Here, the contact plugs 336 have a lower portion and an upper portionwider than the lower portion. Also, the contact plugs 336, have a heightand a width along a length direction of the bit line structures 316longer than the height. In other words, the contact plugs 336 havesubstantially vertical and planar side faces, have a width longer thanits height.

FIGS. 51 to 70 are cross-sectional views illustrating a method ofmanufacturing the contact plug in FIG. 50. FIGS. 51, 53, 55, 57, 59, 61,63, 65, 67, and 69 are cross-sectional views taken along line V-V′ inFIG. 50, and FIGS. 52, 54, 56, 58, 60, 62, 64, 66, 68, and 70 arecross-sectional views taken along line VI-VI′ in FIG. 50.

Referring to FIGS. 51 and 52, the isolation layer 302 is formed in thesemiconductor substrate 300 to define the active region 304. The wordline structures 306 and the contact pads 308 are formed on thesemiconductor substrate 300.

The first insulating interlayer 310 is formed on the contact pads 308and the word line structures 306. A conductive layer (not shown) and acapping layer (not shown) are sequentially formed on the semiconductorsubstrate 300 having the first insulating interlayer 310. The conductivelayer and the capping layer are patterned to form the bit linestructures 316 including the conductive layer pattern 312 and thecapping layer pattern 314. Here, the conductive layer pattern 312includes a barrier metal layer pattern 312 a and a metal layer pattern312 b. Examples of the barrier metal layer pattern 312 a are a titaniumlayer, a titanium nitride layer, a combination thereof, etc. An exampleof the metal layer pattern 312 b is a tungsten layer. An example of thecapping layer pattern 314 is a silicon nitride layer.

Referring to FIGS. 53 and 54, a silicon nitride layer (not shown) isformed on the semiconductor substrate 300 along the bit line structures3 6. The silicon nitride layer is anisotropically etched to form thespacer 318. A second insulating interlayer (not shown) including siliconoxide covers the bit line structures 316 having the spacer 318. Thesecond insulating interlayer is planarized via a CMP process until thebit line structures 316 are exposed. The planarized second insulatinginterlayer is anisotropically etched to form the second insulatinginterlayer pattern 320, partially filling a lower space between the bitline structures 316. Here, the second insulating interlayer pattern 320has an upper face higher than that of the metal layer pattern 312 b.

Referring to FIGS. 55 and 56, the etching stop layer 322 includingsilicon nitride is formed on the bit line structures 316 and the secondinsulating interlayer pattern 320.

Referring to FIGS. 57 and 58, a third insulating interlayer 324 isformed on the etching stop layer 322 to fill the space between the bitline structures 316. The third insulating interlayer 324 and the etchingstop layer 322 are planarized until the bit line structures 316 areexposed to form the preliminary etching stop layer pattern 322 a.

Referring to FIGS. 59 and 60, a mask layer (not shown) includingpolysilicon is formed on the planarized third insulating interlayer 324.The mask layer is patterned to form a mask pattern 326 for definingstorage node contact holes.

Referring to FIGS. 61 and 62, the third insulating interlayer 324 isanisotropically etched using the mask pattern 326 as an etching mask toform the third insulating interlayer pattern 324 a having first holes328 that expose the preliminary etching stop layer pattern 322 a.

Referring to FIGS. 63 and 64, the third insulating interlayer pattern324 a that is exposed through the first holes 328 is partially andisotropically etched by a wet etching process to form the thirdinsulating interlayer pattern 324 b having second holes 330 expandingfrom the first holes 328 in a direction of the bit line structures 316.Here, the third insulating interlayer pattern 324 b partially remainsbetween the second holes 330.

Referring to FIGS. 65 and 66, the preliminary etching stop layer pattern322 a, the first insulating interlayer 310 and the second insulatinginterlayer pattern 320 exposed through the second holes 330 areanisotropically etched to form third holes 332 having a volume smallerthan that of the second holes 330, the first insulating interlayerpattern 310 a, the second insulating interlayer pattern 320 a, and theetching stop layer pattern 322 b. Here, the third holes 332 have anopened upper end narrower than that of the second holes 330. The secondand third holes 330 and 332 are referred to as the storage node contacthole 334.

Referring to FIGS. 67 and 68, the storage node contact hole 334 isfilled with a conductive material. The conductive material and the maskpattern 326 are planarized to form the storage node contact plugs 336.

Referring to FIGS. 69 and 70, the storage node electrode 338 is formedon the storage node contact plug 336. Here, since the storage nodecontact plug 336 has a wide upper face, the storage node electrode 338may be slanted.

Additionally, a dielectric layer (not shown) and a plate electrode (notshown) are formed on the storage node electrode 338 to complete acapacitor.

According to the present invention, since the storage node contact plugshave vertical side faces, the storage node contact plugs have uniformupper widths regardless of the polished amounts, thereby ensuring asufficient overlap margin between the storage node contact plug and thestorage node electrode.

Also, the etching stop layer is used in the wet etching process as wellas the anisotropic etching process for expanding the upper portion ofthe storage node contact hole so that recipes for the wet etchingprocess may be readily selected.

Having described the preferred embodiments of the present invention, itis noted that modifications and variations can be made by personsskilled in the art in light of the above teachings. It is therefore tobe understood that changes may be made in the particular embodiment ofthe present invention disclosed which is within the scope and the spiritof the invention outlined by the appended claims.

1. A semiconductor device comprising: word line structures extending ina first direction on a substrate of which an active region is defined,the word line structures traversing the active region; first and secondcontact pads respectively formed on the active region at both sides ofthe word line structures; bit line structures having contact with thefirst contact pad and extending in a second direction substantiallyperpendicular to the first direction; an insulation layer structureformed on the substrate having the bit line structures; storage nodecontact plugs formed through the insulating layer structure between thebit line structures and having contact with the second contact pad, thestorage node contact plugs having a lower portion and an upper portionwider than the lower portion, and the upper portion of the storage nodecontact plugs extending in the second direction and having side faceperpendicular to the first direction; and storage node electrodes formedon the storage node contact plugs.
 2. The semiconductor device of claim1, wherein the insulation layer structure comprises: a first insulatinginterlayer pattern partially filling a lower space between the bit linestructures; an etching stop layer pattern formed on sidewalls of the bitline structures exposed by the first insulating interlayer pattern; anda second insulating interlayer pattern formed on the etching stop layerpattern to partially fill an upper space between the bit line structuresthat is positioned over the lower space.
 3. The semiconductor device ofclaim 2, wherein the etching stop layer pattern comprises siliconnitride.
 4. The semiconductor device of claim 1, wherein the storagenode electrodes correspond to the storage node contact plug,respectively, the storage node electrodes being arranged in a zigzagpattern so that a line connected between adjacent storage nodeelectrodes are diagonal to the first and second directions.
 5. Thesemiconductor device of claim 1, wherein the storage node contact plugscomprise doped polysilicon.